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146 hd66206 (80-channel column/common driver for middle- or large-sized liquid crystal panel) rev 0.2 february 1996 description the hd66206 is an 80-channel lcd driver, which is used for liquid crystal dot matrix display. this product can drive various types of liquid crystal displays, from small-sized to monochrome vga-s ized displays. since this product can function as a column and a common driver, an lcd panel can be configured only with this product. features logic power supply voltage: 2.7 to 5.5v display duty: 1/16 (1/5 bias) to 1/240 80 liquid crystal display drive circuits liquid crystal display drive voltage: 6 to 28v data transfer speed ? 8 mhz max (at 5-v operation) ? 6.5 mhz max (at 3-v operation) chip enable signal automatic generation standby function controllers that can be used with ? hd64645/hd64646 (lctc series) ? hd66841 (lvic series) packages ? tfp-100b ? no package (bare chip) cmos process
hd66206 147 ordering information type name package HD66206TE tfp-100b hcd66206 bare chip
hd66206 148 pin arrangement HD66206TE (tfp-100b) (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 y53 y54 y55 y56 y57 y58 y59 y60 y61 y62 y63 y64 y65 y66 y67 y68 y69 y70 y71 y72 y73 y74 y75 y76 y77 y27 y26 y25 y24 y23 y22 y21 y20 y19 y18 y17 y16 y15 y14 y13 y12 y11 y10 y9 y8 y7 y6 y5 y4 y3 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 y52 y51 y50 y49 y48 y47 y46 y45 y44 y43 y42 y41 y40 y39 y38 y37 y36 y35 y34 y33 y32 y31 y30 y29 y28 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 y78 y79 y80 e v1 v2 v3 v4 v ee m cl1 gnd shl v cc fcs test dispoff d3 d2 d1r d0l cl2 car y1 y2 figure 1 pin arrangement (HD66206TE)
hd66206 149 block diagram liquid crystal display drive circuit 80-bit latch circuit 80-bit bi-directional shift register (also used as a latch circuit) operating mode switchin circuit selector d0l d1r d2 d3 counter fcs test e car y80y79y78y77y76 y1 v1 v2 v3 v4 m cl1 cl2 test input shl data conversion circuit figure 2 block diagram
hd66206 150 block functions liquid crystal display drive circuit generates one of four levels v1 to v4 to the output pin to drive the liquid crystal display according to the combination of data of the 80-bit latch circuit and the m signal. 80-bit latch circuit latches data of the 80-bit bi-directional shift register (also used as a latch circuit) at the falling edge of cl1, and transmits it to the liquid crystal display drive circuit. 80-bit bi-directional shift register (also used as a latch circuit) when fcs is low, this register functions as an 80-bit shift register. at this time, d0l and d1r are used as data input/output pins. when fcs is high, this register functions as a 20 4-bit unit latch circuit. at this time, data that is input in parallel to data input pin d0l, d1r, d2 and d3 is converted to 4-bit data, and then is latched to this register according to the latch signal generated by the selector. data conversion circuit when fcs is low, d0l and d1r are used as data input/output pins. when fcs is high, d0l, d1r, d2, and d3 are input data. selector decodes output data from the counter and generates a latch signal. functions when latching data at serial-latch operation (when fcs is high). at this time, after 80 bits of data y1 to y80 are completely latched, the operation of the selector terminates. even if input data changes, data in the latch circuit is maintained. operating mode switching circuit switches common driver operation (when fcs is low) and column driver operation (when fcs is high).
hd66206 151 pin function table 1 pin functions classification symbol pin no. pin name input/ output function power supply v cc gnd v ee 39 37 34 v cc gnd v ee v cc C gnd: logic power supply v cc C v ee : power supply for driving the liquid crystal display. v1 v2 v3 v4 30 31 32 33 v1 v2 v3 v4 input power supply voltage for liquid crystal display drive level. see figure 3. control signal cl1 36 clock 1 input column driver data latch signal. data is latched at the falling edge of this signal. set this signal low in common driver operation. cl2 47 clock 2 input in column driver operation, used as a display data latch signal. in common driver operation, used as a line selection data shift signal. in both operations, this signal is valid at its falling edge. m 35 m input ac conversion signal for liquid crystal display drive output. shl 38 shift left input control signal for inverting data output destination. 1. in column driver operation see figure 4. 2. in common driver operation sr1, sr2, sr3, ...., sr80 correspond to y1, y2, y3, ...., y80 outputs. when shl is low, data is input to d0l pin and output from d1r pin. d2 and d3 are set low. when shl is high, the relationships between d0l and d1r are reverse. see table 2. ( 29 enable input when fcs is high, data latch starts by setting the ( signal low. when fcs is low, set the ( signal high. the relationships between the ( signal, the fcs signal, data latch operation, and driver function are as show in table 3
hd66206 152 table 1 pin function (cont) classification symbol pin no. pin name input/ output function control signal &$5 48 carry output when fcs is high, a chip enable signal is transferred to the next ic from this pin. connect this pin to ( of the next ic. when fcs is low, open this pin. ',632)) 42 display off input when this signal is low, liquid crystal display drive output is set at v1 level and liquid crystal display is turned off. at this time, internal display data is not affected. when this signal is high, the operation returns to the normal status. d0l d1l d2 d3 46 45 44 43 data0 (l) data1 (r) data2 data3 input/ output input in column driver operation, input display data to d0l, d1r, d2, and d3 pins. in common driver operation, when shl is high, d0l and d1r pins are display data output and input pins, respectively, and vice versa when shl is low. at this time, set d2 and d3 low. when display data is high, liquid crystal display drive output is selection level and the display is on, and when display data is low, they are non-selection level and off, respectively. fcs 40 function select input control signal to select each operating mode. when the fcs pin is high, the operating mode is column driver, and when it is low, the operation mode is common driver. test 41 test input test pin. set this pin low. liquid crystal display drive output y1 to y80 49 to 100 1 to 28 y1 to y80 output liquid crystal display drive output. one of four levels v1 to v4 is output according to the combination of the m signal and display data. see figures 5 and 6.
hd66206 153 v1 and v2: selection level v3 and v4: non-selection level v1 v3 v4 v2 figure 3 liquid crystal display drive level shl input data and latch address y80 y79 y78 y77 y76 y75 y74 y73 d0l d1r d0l d1r last high y80 y79 y78 y77 y76 y75 y74 y73 d1r d0l d1r d0l 1st 2nd y1 y2 y3 y4 y5 y6 y8 y7 d0l d1r d0l d1r d0l d1r 1st 2nd y1 y2 y3 y4 y5 y6 y8 y7 d3 d2 d1r d0l d3 d2 d1r d0l d0l d1r d2 d3 last low d3 d2 d3 d2 d3 d2 d2 d3 d3 d2 d3 d2 d3 d2 figure 4 column driver operating mode table 2 common driver operation shl shift register shift direction common signal scan direction low d0l ? sr ? sr .......... sr ? d1r 1 2 80 y1 ? y80 high d1r ? sr ? sr .......... sr ? d0l 80 79 1 y80 ? y1 table 3 relationship between fcs, ( ( , data latch operation, and driver function fcs ( ( data latch operation driver function high low enabled column driver high disabled low high common driver
hd66206 154 1 0 11 00 v2 v4 v1 v3 m data output level output level to be selected figure 5 liquid crystal display drive output in column driver operation 1 0 11 00 v1 v4 v2 v3 m data output level output level to be selected figure 6 liquid crystal display drive output in common driver operation
hd66206 155 application examples figure 7 shows an example when configuring the 640 240-dot lcd panel using the hd66206. open gnd v cc v ee e d1r shl dispoff v1 v4 v3 v2 cl2 m fcs test hd66206 (1) d3 d2 cl1 car d0l lcd panel 640 240 1/240 duty com1 com2 com3 com239 com240 seg1 seg2 seg3 seg638 seg639 seg640 v1 v3 v4 v2 cl1 cl2 m d0l, d1r, d2, d3 dispoff fcs test car hd66206 (1) y80, y79, ?y2, y1 80 r1 r2 r1 r1 r1 v cc v cc shl v cc 80 gnd v cc v ee e d1r shl dispoff v1 v4 v3 v2 cl2 m fcs test hd66206 (3) d3 d2 cl1 car d0l y80, y79, ? y2, y1 80 controller flm cl1 m dispoff d0l, d1r, d2, d3 cl2 open open open gnd(0v) v cc (+3v) e gnd v cc v ee v ee (-25v) y80, y79, ? y2, y1 v1 v3 v4 v2 cl1 cl2 m d0l, d1r, d2, d3 dispoff fcs test car hd66206 (2) 80 shl e gnd v cc v ee y80, y79, ? y2, y1 v cc v1 v3 v4 v2 cl1 cl2 m d0l, d1r, d2, d3 dispoff fcs test car hd66206 (8) 80 shl e gnd v cc y80, y79, ? y2, y1 v cc v ee + + + + notes: 1. the resisances of r1 and r2 depend on the type of lcd panel used. for example, for an lcd panel with a 1/15 bias, r1 and r2 must be 3 k and 33 k , respectively. that is, r1/(4?1 + r2) should be 1/15. 2. to stabilize the power supply, place two 0.1- f capacitors near each lcd driver: one between v cc and gnd, and the other between v cc and v ee . . 3. in this example, the y1 pin is located to the right as viewed from the front of the panel. figure 7 application example
hd66206 156 cl2 cl1 d0l seg.4 seg.8 seg.12 seg.16 1 2 3 4 19 20 21 22 23 seg.76 seg.80 seg.84 seg.88 seg.92 156 157 158 159 160 seg.624 seg.628 seg.632 seg.636 seg.640 d1r seg.3 seg.7 seg.11 seg.15 seg.75 seg.79 seg.83 seg.87 seg.91 seg.623 seg.627 seg.631 seg.635 seg.639 d2 seg.2 seg.6 seg.10 seg.14 seg.74 seg.78 seg.82 seg.86 seg.90 seg.622 seg.626 seg.630 seg.634 seg.638 d3 seg.1 seg.5 seg.9 seg.13 seg.73 seg.77 seg.81 seg.85 seg.89 seg.621 seg.625 seg.629 seg.633 seg.637 car (the first ic) the next ic is activated. y1 (the first ic) y80 (the first ic) seg.80 seg.1 ---------- ---------- ---------- ---------- ---------- ----------------------- ----------------------- ----------------------- ----------------------- ----------------------- figure 8 timing charts for application example in column driver operation cl1 12 3 4 237 238 239 240 1 23 4 237 238 239 240 flm m y80 (the first ic) y79 (the first ic) v4 v2 v3 v4 v2 v3 v3 v1 v4 v1 v4 v4 ------------------- ------------------- figure 9 timing charts for application example in common driver operation
hd66206 157 absolute maximum ratings item symbol ratings unit note power supply logic circuit v cc C0.3 to +7.0 v 1 voltage liquid crystal display drive circuit v ee v cc C 30.0 to v cc + 0.3 v input voltage (1) vt1 C0.3 to v cc + 0.3 v 1 and 2 input voltage (2) vt2 v ee C 0.3 to v cc + 0.3 v 1 and 3 operating temperature t opr C20 to +75 c storage temperature t stg C55 to +125 c notes: 1. measured relative to gnd (0v). 2. applies to cl1, cl2, m, shl, ( , d0l, d1r, d2, d3, fcs, test, and ',632)) pins. 3. applies to v1 to v4 pins. 4. if the lsi is used beyond its absolute maximum rating, it may be permanently damaged. it should always be used within the limits of its electrical characteristics in order to prevent malfunction or unreliability.
hd66206 158 electrical characteristics dc characteristics 1 (v cc = 5v 10%, gnd = 0v, v cc C v ee = 6 to 28v, and ta = C20 to 75 c, unless otherwise stated) item symbol applicable pin min. typ. max. unit conditions note input high level voltage vih cl1, cl2, m, shl, ( , d0l, d1r, d2, 0.7 v cc v cc v input low level voltage vil d3, fcs, test, and ',632)) 0 0.3 v cc v output high level voltage voh &$5 , d0l, d1r v cc C 0.4 v i oh = C0.4 ma output low level voltage vol &$5 , d0l, d1r 0.4 v i ol = 0.4 ma vi-yj on resistance r on1 y1 to y80, v1 to v4 2.0 k w i on = 100 m a v cc C v ee = 28v 1 and 5 r on2 4.0 k w 1 and 4 input leakage current (1) i il1 cl1, cl2, m, shl, ( , d0l, d1r, d2, d3, fcs, test, and ',632)) C5 5 m a vin = v cc to gnd input leakage current (2) i il2 v1 to v4 C25 25 m a vin = v cc to v ee consumption current (1) i gnd1 3.0 ma f cl2 = 8.0 mhz f cl1 = 50 khz f m = 2.3 khz 2 and 4 consumption current (2) i st 200 m a v cc = 5v v cc C v ee = 28v 2 to 4 consumption current (3) i ee1 500 m a checker data fcs = high 2 and 4 consumption current (4) i gnd2 100 m af cl1 = 50 khz f m = 2.3 khz 2 and 5 consumption current (5) i ee2 500 m a v cc = 5v v cc C v ee = 28v fcs = low 2 and 5
hd66206 159 dc characteristics 2 (v cc = 2.7 to 4.5v, gnd = 0v, v cc C v ee = 6 to 28v, and ta = C20 to 75 c, unless otherwise stated) item symbol applicable pin min. typ. max. unit conditions note input high level voltage vih cl1, cl2, m, shl, ( , d0l, d1r, d2, 0.8 v cc v cc v input low level voltage vil d3, fcs, test, and ',632)) 0 0.2 v cc v output high level voltage voh &$5 , d0l, and d1r v cc C 0.4 v i oh = C0.4 ma output low level voltage vol &$5 , d0l, and d1r 0.4 v i ol = 0.4 ma vi-yj on resistance r on1 y1 to y80, and v1 to v4 2.0 k w i on = 100 m a v cc C v ee = 2 8v 1 and 5 r on2 4.0 k w 1 and 4 input leakage current (1) i il1 cl1, cl2, m, shl, ( , d0l, d1r, d2, d3, fcs, test, and ',632)) C5 5 m a vin = v cc to gnd input leakage current (2) i il2 v1 to v4 C25 25 m a vin = v cc to v ee consumption current (1) i gnd1 1.5 ma f cl2 = 6.5 mhz f cl1 = 40.6 khz f m = 1.8 khz 2 and 4 consumption current (2) i st 100 m a v cc = 3.0v v cc C v ee = 28v 2 to 4 consumption current (3) i ee1 500 m a checker data fcs = high 2 and 4 consumption current (4) i gnd2 50 m af cl1 = 40.6 khz f m = 1.8 khz 2 and 5 consumption current (5) i ee2 500 m a v cc = 3.0v v cc C v ee = 28v fcs = low 2 and 5 notes: 1. indicates the resistance between one pin from y1 to y80 and another pin from the v pins v1 to v4, when a load current is applied to the y pin; defined under the following conditions: in column driver operation v1 and v3 = v cc C 2/10 (v cc C v ee ) v4 and v2 = v ee + 2/10 (v cc C v ee ) in common driver operation v1 and v3 = v cc C 2/10 (v cc C v ee ) v4 and v2 = v ee + 2/10 (v cc C v ee ) v1 and v3 should be near the vcc level, and v4 and v2 should be near the v ee level. all these voltage pairs should be separated by less than d v, which is the range within which r on , the lcd drive circuits output impedance, is stable. note that d v depends on power supply voltage v cc C v ee . see figure 10.
hd66206 160 2. input and output currents are excluded. when a cmos input is floating, excess current flows from the power supply through to the input circuit. to avoid this, vih and vil must be held to v cc and gnd, respectively. 3. v cc C gnd current at standby ( ( input = high) 4. applies to column driver operation. 5. applies to common driver operation. d v d v v cc v1 v3 v4 v2 v ee 628 2.4 5.6 d v (v) v cc ? ee (v) figure 10 relationship between driver output waveform and level voltages
hd66206 161 pin configuration each pin configuration is shown below. v cc gnd nmos pmos applicable pin: cl1, cl2, shl m, e, fcs, and test applicable pin: d2 and d3 d3 d2 input enable figure 11 input pin configuration applicable pin: d0l and d1r d0l d1r input enable pmos pmos nmos nmos output enable output data v cc gnd pmos pmos nmos nmos output enable output data v cc gnd figure 12 input/output pin configuration v cc gnd nmos pmos applicable pin: car pmos pmos nmos nmos v1 v3 v4 v2 v cc v cc v ee v ee applicable pin: y1?80 yn figure 13 output pin configuration
hd66206 162 ac characteristics 1 (in column driver operation) (v cc = 5v 10%, gnd = 0v, v cc C v ee = 6 to 28v, and ta = C20 to +75 c, unless otherwise stated) item symbol applicable pins min. max. unit note clock cycle time t cyc cl2 125 ns clock high level width t cwh cl2 and cl1 40 ns clock low level width t cwl cl2 40 ns clock setup time t scl cl1 and cl2 80 ns clock hold time t hcl cl1 and cl2 80 ns clock rise time t r cl1 and cl2 1 ns 1 clock fall time t f cl1 and cl2 1 ns 1 data setup time t ds d0l, d1r, d2, d3, and cl2 20 ns data hold time t dh d0l, d1r, d2, d3, and cl2 20 ns enable setup time t esu ( and cl2 20 ns carry output delay time t car &$5 and cl2 70 ns 2 m phase difference t cm m and cl1 300 ns cl1 cycle time t cl1 cl1 t cyc 50 ns
hd66206 163 ac characteristics 2 (in column driver operation) (v cc = 2.7 to 4.5v, gnd = 0v, v cc C v ee = 6 to 28v, and ta = C20 to +75 c, unless otherwise stated) item symbol applicable pins min. max. unit note clock cycle time t cyc cl2 152 ns clock high level width t cwh cl2 and cl1 65 ns clock low level width t cwl cl2 65 ns clock setup time t scl cl1 and cl2 80 ns clock hold time t hcl cl1 and cl2 120 ns clock rise time t r cl1 and cl2 1 ns 1 clock fall time t f cl1 and cl2 1 ns 1 data setup time t ds d0l, d1r, d2, d3, and cl2 50 ns data hold time t dh d0l, d1r, d2, d3, and cl2 50 ns enable setup time t esu ( and cl2 30 ns carry output delay time t car &$5 and cl2 100 ns 2 m phase difference t cm m and cl1 300 ns cl1 cycle time t cl1 cl1 t cyc 50 ns notes: 1. clock rise time (t r ) and clock fall time (t f ) must satisfy the following conditions: t r and t f < (t cyc C t cwh C t cwl )/2 t r and t f 50 2. defined by connecting the load circuit shown in figure 14. 30 pf test point figure 14 load circuit
hd66206 164 ac characteristics 3 (in common driver operation) (v cc = 2.7 to 5.5v, gnd = 0v, v cc C v ee = 6 to 28v, and ta = C20 to +75 c, unless otherwise stated) item symbol applicable pins min. max. unit note clock cycle time t cyc cl2 10 m s clock high level width t cwh cl2 80 ns clock low level width t cwl cl2 1.0 m s clock rise time t r cl2 30 ns clock fall time t f cl2 30 ns data setup time t ds d0l, d1r, and cl2 100 ns data hold time t dh d0l, d1r, and cl2 100 ns data output delay time t dd d0l, d1r, and cl2 7.0 m s1 note: defined by connecting the load circuit shown in figure 15. 30 pf test point figure 15 load circuit
hd66206 165 cl2 d0l, d1r, d2, and d3 cl1 cl2 t r t cwh t f t cwl t cyc t ds t dh t cwh t scl t hcl last data t car t esu v oh car e v ih v il v ih v il v ih v il v ih v il vil t car v ol t cl1 m v ih v il t cm figure 16 common driver operation timing
hd66206 166 cl2 (d0l, d1r) (d0l, d1r) t cwh t f t cwl v ih v il t ds t dh v ih v il v oh v ol data in data out t r t dd t cyc figure 17 common driver operation timing

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